During the operation of integrated circuits, when erasing flash memory elements, high voltages are applied to the die of the integrated circuit, e.g., to the doping well, e.g., a p-type well of the memory array.
Due to electrical couplings such as, e.g., alternating-current couplings or, e.g., capacitive couplings during erasure with high voltages, the floating interconnects such as bit lines that are arranged above a doping well are at a correspondingly high potential.
The bit lines are coupled for the purpose of coupling the memory cells to, e.g., read-out circuits with multiplexers that are arranged outside the memory array and thus above a further doping well, and occupy a relatively large area of the die of the integrated circuit.
If a multiplexer output is at a low potential, e.g., at 0 volts, then high electric fields that can exceed the breakdown field strength occur between adjacent lines of the inputs and outputs of the multiplexer switching elements coupled to the different bit lines.
FIG. 1 shows a plan view of a 2:1 multiplexer in accordance with the prior art. The illustration shows a first switching element 101 and a second switching element 102, wherein the first switching element 101 is coupled by the input to the first bit line 104 and the second switching element 102 is coupled by the input to the second bit line 105. The switching elements 101 and 102 of the multiplexer, which are larger than the memory elements, are arranged in offset fashion (stacked) in order to save space, or in order to be adapted to the distance between the conductive structures such as the bit lines. The bit lines 104, 105 are arranged above the switching elements and the bit lines 104, 105 are coupled to the switching elements by means of contact vias.
The output of the first switching element 101 is coupled to the first bit line section 106 and the output of the second switching element 102 is coupled to the second bit line section 107. The output of the first switching element 101 is coupled by means of an electrical connection 108 to the output of the second switching element 102 and to an output 109.
Depending on the driving of the switching elements 101, 102, the first bit line 104 or the second bit line 105 can be coupled to the output 109.
During the erasure of the memory elements, the first bit line 104 and the second bit line 105 are at a high potential, e.g., as a result of the capacitive coupling or AC voltage coupling. A low potential, e.g., 0 volts is present at the output 109.
In the case of the geometric arrangement of the components shown (i.e., device stacking), a region, identified by the area 103, is present in which the electric field can be particularly high due to the high potential present on the second bit line 105 and the low potential present on the first bit line section 106.
Primarily if the pitch spacings of the integrated circuit are reduced for the purpose of miniaturizing the structures, the breakdown field strength can be exceeded in such a region indicated by the area 103.